ASIC/FPGA Verification

SSN is seeking candidates who have a proven track record on driving strategies and successful verification execution on high-performance IPs and/ or SoC designs. Candidates who are strong team players with good communication and leadership skills and who are able to positively and strategically influence the FPGA design teams with an eye towards improving overall product quality.

Skills we are looking for:

ASIC /FPGA workflow knowledge of verification and has experience of at least 5 years.

Good Debugging skills.

Must be aware of verification sign-off methodology. Like Functional /code coverage concept, writing vPlan, writing verification specification, verification report etc.

Skills we are looking for:

ASIC /FPGA workflow knowledge of verification and has experience of at least 5 years.

Good Debugging skills.

Must be aware of verification sign-off methodology. Like Functional /code coverage concept, writing vPlan, writing verification specification, verification report etc.

Must have EDA tool experience on either of them Questasim or NCSIM or VCS.

Must have used system Verilog for verification for at least 5 years.

Must have used UVM methodology for at least 3 years.