Jobs

ASIC /FPGA Design

SSN is seeking ASIC/ FPGA Design Engineers to design and implement SoC’s. This position offers the opportunity to have a real impact in a dynamic, technology-focused environment. You will be working with a dynamic team of outstanding professionals stretching around the globe.

Skills we are looking for:

ASIC/FPGA workflow for knowledge of Design and has experience of at least 5 years.

Good Debugging skills.

Must have EDA tool experience on Questasim or NCSIM and spyglass.

Must have the understanding of synthesis.

Must have used either System Verilog or Verilog or VHDL for design.

ASIC/FPGA Verification

SSN is seeking candidates who have a proven track record on driving strategies and successful verification execution on high-performance IPs and/ or SoC designs. Candidates who are strong team players with good communication and leadership skills and who are able to positively and strategically influence the FPGA design teams with an eye towards improving overall product quality.

Skills we are looking for:

ASIC /FPGA workflow knowledge of verification and has experience of at least 5 years.

Good Debugging skills.

Must be aware of verification sign-off methodology. Like Functional /code coverage concept, writing vPlan, writing verification specification, verification report etc.

Contact Us

Company address
Semicon Service Nordic AB
Huvudstagatan 4
SE-17158 Solna
Corporates
Would you like us to assist in your search for premium talent?
Phone: +46 767 524 305
E-mail: info@semiconservicenordic.com

Skills we are looking for:

ASIC/FPGA workflow for knowledge of Design and has experience of at least 5 years.

Good Debugging skills.

Must have EDA tool experience on Questasim or NCSIM and spyglass.

Must have the understanding of synthesis.

Must have used either System Verilog or Verilog or VHDL for design.

Skills we are looking for:

ASIC /FPGA workflow knowledge of verification and has experience of at least 5 years.

Good Debugging skills.

Must be aware of verification sign-off methodology. Like Functional /code coverage concept, writing vPlan, writing verification specification, verification report etc.

Must have EDA tool experience on either of them Questasim or NCSIM or VCS.

Must have used system Verilog for verification for at least 5 years.

Must have used UVM methodology for at least 3 years.

Contact Us