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Home
About Us
Why Semicon Service Nordic
Leadership Team
Services
Services to Employee
Services to Customer
Industry Practices
Design
Verification
Management
SOC Architects
Jobs
ASIC/FPGA Design
ASIC/FPGA Verification
Contact Us
LinkedIn
Good Debugging skills.
Must have EDA tool experience on either of them Questasim or NCSIM or VCS.
Must be aware of verification sign-off methodology. Like Functional /code coverage concept, writing vPlan, writing verification specification, verification report etc.
Must have used UVM methodology for at least 3 years.
Must have used system Verilog for verification for at least 5 years.
ASIC /FPGA workflow knowledge of verification and has experience of at least 5 years.
